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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SP6136 데이터시트(PDF) 7 Page - Sipex Corporation |
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SP6136 데이터시트(HTML) 7 Page - Sipex Corporation |
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7 / 18 page  7 Oct 3-06 Rev L SP636 Synchronous Buck Controller © 2006 Sipex Corporation THEORY OF OPERATION MHz) and enough gain (60 dB) to run Type III compensation schemes with adequate gain andphasemarginsatcrossoverfrequencies greater than 200 kHz. The common mode output of the error ampli- fier (COMP) is 0.9V to 2.2V. Therefore, the PWM voltage ramp has been set between .0V and 2.0V to ensure proper 0% to 00% duty cycle capability. The voltage loop also includes two other very important features. One is a non-synchronous start up mode. Basically, the GL driver cannot turn on unless the GH driver has attempted to turn on or the SS pin has exceeded .7V. This feature prevents the controller from “dragging down” the output voltage during startup or in fault modes. The second feature is a 00% duty cycle timeout that ensures synchronized refreshing of the BST capacitor at very high duty ratios. In the event that the GH driver is on for 20 continuous clock cycles, a reset is given to the PWM flip flop half way through the 20th cycle. This forces GL to rise for the remainder of the cycle, in turn refreshing the BST capacitor. Gate Drivers The SP636 contains a pair of powerful 2 W Pull-up and .5 W Pull-down drivers. These state-of-the-art drivers are designed to drive an external NFET capable of handling up to 30A. Rise, fall, and non-overlap times have all been minimized to achieve maximum efficiency. All drive pins GH, GL, & SWN are monitored continuously to ensure that only one external NFET is ever on at any given time. Thermal & Short-Circuit Protection Because the SP636 is designed to drive large NFETs running at high current, there is a chance that either the controller or power converter will become too hot. Therefore, an internal thermal shutdown (145°C) has been included to prevent the IC from malfunction- ing at extreme temperatures. Over-Current Protection Over-current is detected by monitoring a differential voltage across the output in- ductor as shown in figure 1. Inputs to an over-current detection comparator, set to trigger at 60 mV nominal, are connected to the inductor as shown. Since the average voltage sensed by the comparator is equal to the product of in- ductor current and inductor DC resistance (DCR) then Imax = 60mV / DCR. Solving this equation for the specific inductor in cir- cuit , Imax = 4.6A. When Imax is reached, a 220 ms time-out is initiated, during which top and bottom drivers are turned off. Fol- lowing the time-out, a restart is attempted. If the fault condition persists, then the time- out is repeated (referred to as hiccup). Figure 1: Over-current detection circuit ISN SP613X SWN ISP Vout L = 2.7uH, DCR = 4.mOhm RS 5. 11K RS2 5. K CS 0.uF CSP 6.8nF |
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