6.42

IDT70P256/246L

Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM

Industrial Temperature Range

13

IDT70P256/246L

Preliminary

Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM

Industrial Temperature Range

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range

NOTES:

1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Read With

BUSY.

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual).

4. To ensure that a write cycle is completed after contention.

70P256/246

Ind'l Only

Symbol

Parameter

Min.

Max.

Unit

BUSY TIMING

tBAA

BUSY Access Time from Address Match

____

45

ns

tBDA

BUSY Disable Time from Address Not Matched

____

45

ns

tBAC

BUSY Access Time from Chip Enable LOW

____

45

ns

tBDC

BUSY Disable Time from Chip Enable HIGH

____

45

ns

tAPS

Arbitration Priority Set-up Time

(2)

5

____

ns

tBDD

BUSY Disable to Valid Data(3)

____

40

ns

tWH

Write Hold After

BUSY(4)

35

____

ns

PORT-TO-PORT DELAY TIMING

tWDD

Write Pulse to Data Delay(1)

____

80

ns

tDDD

Write Data Valid to Read Data Delay

(1)

____

65

ns

5699 tbl 13