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DM9000A
Ethernet Controller with General Processor Interface
Preliminary datasheet
21
Version: DM9000A-DS-P03
Apr. 21, 2005
4
ONEPM
PH0,RW
One Packet Mode
When set, only one packet transmit command can be issued before transmit
completed.
When cleared, at most two packet transmit command can be issued before
transmit completed.
3~0
IFGS
PH0,RW
Inter-Frame Gap Setting
0XXX: 96-bit
1000: 64-bit
1001: 72-bit
1010:80-bit
1011:88-bit
1100:96-bit
1101:104-bit
1110: 112-bit
1111:120-bit
6.26 Operation Test Control Register ( 2EH )
Bit
Name
Default
Description
7~6
SCC
PH0,RW
System Clock Control
Set the internal system clock.
00: 50Mhz
01: 20MHz
10: 100MHz
11: Reserved
5
RESERVED
PH0,RW
Reserved
4
SOE
PH0,RW
Internal SRAM Output-Enable Always ON
3
SCS
PH0,RW
Internal SRAM Chip-Select Always ON
2~0
PHYOP
PH0,RW
Internal PHY operation mode for testing
6.27 Special Mode Control Register ( 2FH )
Bit
Name
Default
Description
7
SM_EN
PH0,RW
Special Mode Enable
6~3
RESERVED
PH0,RW
Reserved
2
FLC
PH0,RW
Force Late Collision
1
FB1
PH0,RW
Force Longest Back-off time
0
FB0
PH0,RW
Force Shortest Back-off time
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