CYT4DNJBJS datasheet(115/209 Pages) INFINEON

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Datasheet

115

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

SID660C VIH_CMOS

Input voltage HIGH

threshold in CMOS

mode

0.7 × V

DDIO_GPIO

––

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0>= 0b0

CFG_IN/VTRIP_SEL<0:0> = 0b0

SID661C VIH_TTL

Input voltage HIGH

threshold in TTL

mode

2.0

–

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0>= 0b0

CFG_IN/VTRIP_SEL<0:0> = 0b1

SID662C VIH_AUTO

Input voltage HIGH

threshold in AUTO

mode

0.8 × V

DDIO_GPIO

––

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0>= 0b1

CFG_IN/VTRIP_SEL<0:0> = 0b0

4.5 V  VDDIO_GPIO  5.5 V

SID663C VIL_CMOS

Input voltage LOW

threshold in CMOS

mode

–

0.3 ×

DDIO_GPIO

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0>= 0b0

CFG_IN/VTRIP_SEL<0:0> = 0b0

SID664C VIL_TTL

Input voltage LOW

threshold in TTL

mode

––

0.8

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0>= 0b0

CFG_IN/VTRIP_SEL<0:0> = 0b1

SID665C VIL_AUTO

Input voltage LOW

threshold in AUTO

mode

–

0.5 ×

DDIO_GPIO

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0>= 0b1

CFG_IN/VTRIP_SEL<0:0> = 0b0

4.5 V  VDDIO_GPIO  5.5 V

SID666C VHYST_CMOS Hysteresis in CMOS

mode

0.05 ×

DDIO_GPIO

––

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0>= 0b0

CFG_IN/VTRIP_SEL<0:0> = 0b0

SID668C VHYST_AUTO Hysteresis in AUTO

mode

0.05 ×

DDIO_GPIO

––

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0>= 0b1

CFG_IN/VTRIP_SEL<0:0> = 0b0

4.5 V  VDDIO_GPIO  5.5 V

SID669C CIN

Input pin capaci-

tance

––

pF Test condition: 10/100MHz

SID670C IIL

Input leakage current

–1

–

µA VDDIO_GPIO = VDDD = 5.5 V,

VSS < VI < VDDIO_GPIO

–40 °C  TA  105 °C

SID671C tR_F_FAST

Rise time or fall time

(10% to 90% of

VDDIO_GPIO)

1–

ns 20 pF load,

CFG_OUT/DRIVE_SEL<1:0> =

0b00,

CFG_OUT/SLOW<0:0> = 0b0,

entire VDDIO_GPIO range

SID672C tR_F_FAST

Rise time or fall time

(10% to 90% of

VDDIO_GPIO)

1–

ns 50 pF load,

CFG_OUT/DRIVE_SEL<1:0> =

0b00,

CFG_OUT/SLOW<0:0> = 0b0,

entire VDDIO_GPIO range,

Guaranteed by design

SID673C tR_F_FAST

Rise time or fall time

(10% to 90% of

VDDIO_GPIO)

1–

ns 20-pF load,

CFG_OUT/DRIVE_SEL<1:0> =

0b01, CFG_OUT/SLOW<0:0> =

0b0, entire VDDIO_GPIO range,

Guaranteed by design

SID674C tR_F_FAST

Rise time or fall time

(10% to 90% of

VDDIO_GPIO)

1–

ns 10-pF load,

CFG_OUT/DRIVE_SEL<1:0> =

0b10, CFG_OUT/SLOW<0:0> =

0b0, entire VDDIO_GPIO range,

Guaranteed by design

SID675C tR_F_FAST

Rise time or fall time

(10% to 90% of

VDDIO_GPIO)

1–

ns 6-pF load,

CFG_OUT/DRIVE_SEL<1:0> =

0b11, CFG_OUT/SLOW<0:0> =

0b0, entire VDDIO_GPIO range,

Guaranteed by design

Table 26-5

I/O specifications (continued)

Spec ID Parameter

Description

Min

Typ

Max

Units

Details/conditions

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