AT75C datasheet(21/171 Pages) ATMEL

21 / 171 page

AT75C DSP Subsystem

1368C–INTAP–08/02

Figure 8. Data Memory Diagram

Memory Addressing

Modes

There are five data memory addressing modes.

Short Direct Addressing Mode Eight bits embedded in the instruction opcode as LSBs plus eight bits from status regis-

ter ST1 as MSB (see “Status Registers” on page 23) compose the 16-bit address to the

data memory. The pages are thus of 256 words each. For example, page 0 corresponds

to addresses 0 to 255 in X-RAM, page 1 from 250 to 511 in X-RAM and page 255 from -

256 to -1 in Y-RAM. Any memory location in the 64K-word data space can be directly

accessed in a single cycle.

Long Direct Addressing Mode

Sixteen bits embedded in the instruction opcode as the second word of the instruction

are used as the 16-bit address of the data memory. Any memory location in the 64K-

word data space can be directly accessed in two cycles.

Indirect Addressing Mode

The Rn registers of the DAAU are used as 16-bit addresses for indirect addressing the

X-RAM and the Y-RAM. Some instructions use two registers, simultaneously address-

ing a memory location in X-RAM and another in Y-RAM, both addressed in indirect

addressing mode.

Short Index Addressing Mode

The base register RB plus an index value (offset7, a 7-bit immediate value embedded in

the instruction opcode) are used for index-based indirect addressing the X-RAM or Y-

RAM. The index value can be from -64 to +63. The actual address is RB + offset7, but

leaving the contents of RB unaffected. For details, refer to “Index Modifier” on page 16.

On-core

Y-RAM

OCEM

CODEC

DPMB

Off-core on-chip

X-RAM

(Data RAM)

On-core

X-RAM

0x0000

0x0800

0x4000

0xE000

0xEC00

0xF000

0xF800

0xFFFF

0x8000

16K

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