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AM79C874VC 데이터시트(PDF) 28 Page - Advanced Micro Devices

부품명 AM79C874VC
상세설명  NetPHY-1LP Low Power 10/100-TX/FX Ethernet Transceiver
PDF  60 Pages
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제조업체  AMD [Advanced Micro Devices]
홈페이지  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM79C874VC 데이터시트(HTML) 28 Page - Advanced Micro Devices

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Am79C874
P R E L I M INARY
PHY CONTROL AND MANAGEMENT
BLOCK (PCM BLOCK)
Register Administration for 100BASE-X
PHY Device
The management interface specified in Clause 22 of
the IEEE 802.3u standard provides for a simple two
wire, serial interface to connect a management entity
and a managed PHY for the purpose of controlling the
PHY and gathering status information. The two lines
are Management Data Input/Output (MDIO), and Man-
agement Data Clock (MDC). A station management
entity which is attached to multiple PHY entities must
have prior knowledge of the appropriate PHY address
for each PHY entity.
Description of the Methodology
The management interface physically transports man-
agement information across the MII. The information is
encapsulated in a frame format as specified in Clause
22 of IEEE 802.3u draft standard and is shown in
Table 6.
Table 6.
Clause 22 Management Frame Format
The PHYAD field, which is five bits wide, allows 32
unique PHY addresses. The managed PHY layer de-
vice that is connected to a station management entity
via the MII interface has to respond to transactions
addressed to the PHY address. A station management
entity attached to multiple PHYs, such as in a managed
802.3 Repeater or Ethernet switch, is required to have
prior knowledge of the appropriate PHY address. See
Table 7 and Figure 7.
Table 7.
PHY Address Setting Frame Structure
Figure 7.
PHY Management Read and Write Operations
PRE
ST
OP
PHYAD
REGADD
TA
DATA
IDLE
READ
1.1
01
10
AAAAA
RRRRR
Z0
D...........D
Z
WRITE
1.1
01
01
AAAAA
RRRRR
10
D...........D
Z
PRE
ST
OP
PHYAD
REGADD
TA
DATA
IDLE
READ
1.1
01
10
00000
RRRRR
Z0
XXXXXXXXXPPAAAAA
Z
WRITE
1.1
01
01
00000
RRRRR
10
XXXXXXXXXPPAAAAA
Z
Idle
Start
Opcode
(Read)
PHY Address
16h, Port 2
Register Address
MII Status, 1h
TA
Register Data
Idle
z
z
z
MDC
MDIO
(PHY)
MDIO
(STA)
z
z
0
1
1
0
1
0
1
1
0
0
0
0
0
1
0
0
1
1
0
0
00
010
0
0
0
0
1
0
z
z
Read Operation
Idle
Start
Opcode
(Write)
PHY Address
16h, Port 2
Register Address
MII Control, 0h
TA
Register Data
Idle
z
z
MDC
MDIO
(STA)
z
01
01
1
0
1
1
00
0
0
0
0
1
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
z
Write Operation
22235I-9



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