AD6654BBCZ datasheet(55/88 Pages) AD

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AD6654

Rev. 0 | Page 55 of 88

MASTER/SLAVE PCLK MODES

The parallel ports can operate in either master or slave mode.

The mode is set via PCLK master mode bit in the Parallel Port

Control 2 register. The parallel ports power up in slave mode to

avoid possible contentions on the PCLK pin.

In master mode, PCLK is an output derived by dividing

PLL_CLK down by the PCLK divisor. The PCLK divisor can

have a value of 1, 2, 4, or 8, depending on the 2-bit PCLK

divisor word setting in the Parallel Port Control 2 register. The

highest PLCK rate in master mode is 200 MHz. Master mode is

selected by setting the PCLK master mode bit in the Parallel

Port Control 2 register.

divisor

PCLK

rate

CLK

PLL

rate

PCLK

In slave mode, external circuitry provides the PCLK signal.

Slave mode PCLK signals can be either synchronous or

asynchronous. The maximum slave mode PCLK frequency is

also 200 MHz.

PCLK

tDPREQ

PxREQ

PxACK

tDPP

Px [15:0]

I [15:8]

Q [15:8]

PxIQ

tDPIQ

PxCH [2:0]

PxCH [2:0] = CHANNEL #

tDPCH

0000 +

GAIN [11:0]

PxGAIN

tDPGAIN

Figure 60. Parallel I/Q Mode with an AGC Gain Word

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