ICS95V157

0501C—11/24/08

Block Diagram

2.5V Single-Ended to SSTL_2 Clock Driver (45MHz - 233MHz)

Pin Configuration

48-Pin TSSOP

Recommended Application:

Single-ended clock input with zero delay board fan out

Product Description/Features:

•

Low skew, low jitter PLL clock driver

•

1 to 10 differential clock distribution (SSTL_2)

•

Feedback pin for input to output synchronization

•

PD# for power management

•

Spread Spectrum tolerant inputs

Switching Characteristics:

•

CYCLE - CYCLE jitter: <60ps

•

OUTPUT - OUTPUT skew: <60ps

•

Period jitter: ±30ps

•

DUTY CYCLE: 49.5% - 50.5%

Functionality

6.10 mm. Body, 0.50 mm. pitch = TSSOP

S

T

U

P

N

IS

T

U

P

T

U

O

e

t

a

t

S

L

L

P

D

D

V

A#

D

PT

N

I

_

K

L

CT

K

L

CC

K

L

CT

T

U

O

_

B

F

D

N

GH

L

L

H

L

f

f

o

/

d

e

s

s

a

p

y

B

D

N

G

HHH

L

H

f

f

o

/

d

e

s

s

a

p

y

B

V

5

.

2

)

m

o

n

(

LL

Z

Z

Z

f

f

o

V

5

.

2

)

m

o

n

(

LH

Z

Z

Z

f

f

o

V

5

.

2

)

m

o

n

(

HL

L

H

L

n

o

V

5

.

2

)

m

o

n

(

HHH

L

H

n

o