ICS527-04

CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB

PECL ZDB AND MULTIPLIER/DIVIDER

IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB

4

ICS527-04

REV F 051310

of dividers are available, then the lowest numbers

should be used. In this example, the output divide (OD)

should be selected to be 2. Then R6:R0 is 0000010,

F6:F0 is 0000011 and S1:S0 is 00.

If you need assistance determining the optimum divider

settings, please send an e-mail to ics-mk@icst.com

with the desired input clock and the desired output

frequency.

Typical Example

The following connection diagram shows the implementation of the example from the previous section.

This will generate a 50 MHz clock synchronously with a 40 MHz input. The layout diagram below will

produce the waveforms shown on the bottom of the example.

F6

FBPECL

F5

F4

GND

F3

PECLIN

PECLIN

F0

F1

F2

PECL

PECL

GND

S1

VDD

R0

VDD

IRANGE

S0

R2

R1

R5

R6

R4

R3

FBPECL

RES

0.01 F

0.01 F

VDD

40 MHz

560

50 MHz

180

PECL output resistor network (50 ohm) is not

shown, but is identical to PECL

VDD

40 MHz

40 MHz

(PECLIN shown)

50 MHz PECL

50 MHz PECL