Nexperia

74ALVC02

Quad 2-input NOR gate

12. Abbreviations

Table 10. Abbreviations

Acronym

Description

CMOS

Complementary Metal-Oxide Semiconductor

DUT

Device Under Test

ESD

ElectroStatic Discharge

HBM

Human Body Model

MM

Machine Model

TTL

Transistor-Transistor Logic

13. Revision history

Table 11. Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

74ALVC02 v.5

20210714

Product data sheet

-

74ALVC02 v.4

Modifications:

• Section 10: Maximum propagation delay (tpd(max)) at VCC = 2.7 V changed to 3.1 ns. (errata)

74ALVC02 v.4

20210430

Product data sheet

-

74ALVC02 v.3

Modifications:

• Section 2: Reference to JESD36 removed.

• Section 7: Derating values for Ptot total power dissipation have been updated.

• Section 8: Maximum output voltage (power-down mode) changed from 4.6 V to 3.6 V (errata).

74ALVC02 v.3

20170907

Product data sheet

-

74ALVC02 v.2

Modifications:

• The format of this data sheet has been redesigned to comply with the identity guidelines of

Nexperia.

• Legal texts have been adapted to the new company name where appropriate.

74ALVC02 v.2

20030714

Product specification

-

74ALVC02 v.1

74ALVC02 v.1

20030205

Product specification

-

-

74ALVC02

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 5 — 27 July 2021

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