ICS1894-32 datasheet(14/51 Pages) RENESAS

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ICS1894-32

10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

PHYCEIVER

IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32

REV M 021512

If a crystal is used as the clocking source, connect it to both

the REFIN (pin 30) and REFOUT (pin 29) pins of the

ICS1894-32. A pair of bypass capacitors on either side of

the crystal are connected to ground. The crystal is used in

the parallel resonance or anti-resonance mode. The value

of the load caps serve to adjust the final frequency of the

crystal oscillation. Typical applications would use 25 pF load

caps. The exact value will be affected by the board routing

capacitance on REFIN and REFOUT pins. Smaller load

capacitors raise the frequency of oscillation.

Once the exact value of load capacitance is established it

will be the same for all boards using the same specification

crystal. The best way to measure the crystal frequency is to

measure the frequency of TXCLK (pin 22) using a frequency

counter with a 1 second gate time. Using the buffered output

TXCLK prevents the crystal frequency from being affected

by the measurement. The crystal specification is shown in

the 25MHz Crystal Specification table.

25 MHz Crystal Specification Table

25 MHz Oscillator Specification table

50 MHz Oscillator Specification table

Status Interface

The ICS1894-32 has two multi-function configuration pins

that report the PHY status by providing signals that are

intended for driving LEDs. Configuration is set by Bank0

Specifications

Symbol Minimum

Typical Maximum

Unit

Fundamental Frequency

24.99875 25.00000

25.00125

MHz

Freq. Tolerance

ΔF/f

± 50

ppm

Input Capacitance

Cin

Specifications

Symbol Minimum

Typical Maximum

Unit

Output Frequency

24.99875 25.00000

25.00125

MHz

Freq. Stability (including aging)

ΔF/f

± 50

ppm

Duty cycle CMOS level one-half VDD

Tw/T

VIH

2.79

Volts

VIL

0.33

Volts

Specifications

Symbol Minimum

Typical Maximum

Unit

Output Frequency

49.9975 50.00000

50.0025

MHz

Freq. Stability (including aging)

ΔF/f

± 50

ppm

Duty cycle CMOS level one-half VDD

Tw/T

VIH

2.79

Volts

VIL

0.33

Volts

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