INGT165B / INGR165B
10/2003 - rev. 2.0
14 of 21
4.3.5
Transmitter and Receiver Timing Parameters
(under recommended operating conditions)
Parameter
Description
Min.
Typ.
Max.
Unit
t1
Setup time PDATA and PARITY to RDCLK rising edge
9
6
ns
t2
VALID active to first rising RDCLK edge
9
12
14
ns
t2-1
VALID high state
5
4
ns
t2-2
LOCK# / RESET# high state before Tx operational
50
µs
t3
PDATA and PARITY hold time
9
6
ns
t4
RDCLK cycle time (without assertion of FLAGI)
30.3
ns
t5
Rising RDCLK edge to sampling window for VALID state
(VALID=0: exit BURST mode,
VALID=1: continue BURST mode)
18
20
22
ns
t6
Setup time PDATA and PARITY to RDCLK rising edge
9
6
ns
t7
VALID active to rising RDCLK edge
9
12
14
ns
t7-1
VALID high state
5
4
ns
t7-2
LOCK# / RESET# high state before TX operational
50
µs
t8
PDATA and PARITY hold time
9
6
ns
t9
RDCLK high state (without assertion of FLAGI)
14
15
16
ns
t10
Rising RDCLK edge to sampling window for VALID state
(VALID=0: continue single word mode,
VALID=1: enter BURST mode)
18
20
22
ns
t11
Rising edge WRCLK to PDATA and PARITY bit valid
1
4
ns
t12
WRCLK cycle time (without assertion of FLAGI)
30.3
ns
t13
Rising edge WRCLK to PDATA and PARITY valid
1
4
ns
t14
WRCLK high state
14
15
16
ns
t15
Rising edge of RDCLK to rising edge of FLAGI
0
18
ns
t16
FLAGI minimum high state
4
6
ns
t17
FLAGI minimum low state
4
6
ns
t18
RDCLK cycle time after assertion of FLAGI (one cycle only)
36
ns
t19
Rising edge of WRCLK to PDATA, PARITY and FLAGI valid
1
4
ns
t20
WRCLK cycle time for data word marked by FLAGO toggle
36
ns
t21
Rising edge of WRCLK after the corrupt data word to rising
edge of LSYNC#
1
5
ns
t22
Rising edge of WRCLK marking the corrupt data word to falling
edge of PERR#
3
6
ns
t23
Rising edge of WRCLK marking the corrupt data header to
rising edge of LSYNC#
0
13
ns
t24
Rising edge of WRCLK marking the corrupt data header to
falling edge of PERR#
1,5
ns
t25
PERR # low state
3
ns
Table 14: Transmitter and Receiver Timing Parameters (under recommended operating conditions)
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