2

ICS9169-01

Pin Configuration

Pin Descriptions

Functionality

*VCO range is limited from 60 - 200 MHz

Note 1: BCLK buffers cannot be supplied with 5 volts (pins 14 and 20) if CPU and fixed frequencies (pins 1, 8, and 26) are being

supplied with 3.3 volts

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

2X1

IN

XTAL or external reference frequency input. This input includes XTAL load

capacitance and feedback bias for a 12.16 MHz crystal, nominally 14.31818

3

X2

OUT

XTAL output which includes XTAL load capacitance.

4, 11, 23

GND

PWR

Ground for logic, PCLK and fixed frequency output buffers.

17

GND

PWR

Ground for BCLK output buffers.

1, 8, 26

VDD

PWR

Power for logic, PCLK and fixed frequency output buffers.

14, 20

VDD

PWR

Power for BCLK output buffers.

6, 7, 9, 10

PCLK(0:3)

OUT

Processor clock outputs which are a multiple of the input reference frequency

as shown in the table above.

13, 12

FS(0:1)

IN

Frequency multiplier select pins. See table above. These inputs have internal

pull-up devices.

15, 16, 18

19, 21, 22

BCLK(0:5)

OUT

Bus clock outputs are fixed at 1/2 the PCLK frequency.

5

OEN

IN

OEN tristates all outputs when low. This input has an internal pull-up device.

24

48MHz

OUT

Fixed 48 MHz clock (with 14.318 MHz input).

28, 27, 25

REF(0:2)

OUT

REF is a buffered copy of the crystal oscillator or reference input clock,

nominally 14.31818 MHz.

PCLK(0:3)

BCLK(0:5)

48 MHz

VCO/2

PCLK/2

48 MHz

TCLK/2

TCLK/4

TCLK/2

28 Pin SOIC

28 Pin SSOP

FS1

FS0

*VCO

X1, REF

(MHz)

PCLK(0:3)

(MHz)

0

0

230/33x X1

14.31818

50 (49.7)

0

1

212/23x X1

14.31818

66 (66.5)

1

0

176/21x X1

14.31818

60 (59.9)

1

1

Test mode

TCLK

TCLK/2