ADIS16203SLASHPCBZ datasheet(12/28 Pages) AD

12 / 28 page

ADIS16203

Rev. 0 | Page 12 of 28

BASIC OPERATION

The ADIS16203 is designed for simple integration into industrial

system designs, requiring only a 3.3 V power supply and a 4-wire,

industry standard SPI. The SPI port facilitates all data transfers

with the ADIS16203’s registers. Each ADIS16203 function (output

data and programming control) has its own register that contains

two bytes of data, and each byte of data has its own unique bit

map. These two bytes are referred to as upper and lower bytes,

and each has its own 6-bit address.

SERIAL PERIPHERAL INTERFACE (SPI)

The ADIS16203’s SPI port provides a common interface that is

supported by a wide variety of digital platforms, including MCUs,

DSPs, and FPGAs. Even when a dedicated port is not available, the

SPI can be implemented using manual bit manipulation, which is

more commonly known as bit banging. The purpose of this section is

to provide a basic description of SPI operation in the ADIS16203.

Please refer to Table 2, Figure 2, and Figure 3 for detailed timing

and operation of this port.

The ADIS16203’s SPI port includes four signals: chip select

(CS), serial clock (SCLK), data input (DIN), and data output

(DOUT). The CS line enables the ADIS16203’s SPI port and, in

effect, frames each SPI event. When this signal is high, the DOUT

lines are in a high impedance state and the signals on DIN and

SCLK have no impact on operation. A complete data frame contains

16 clock cycles. Because the SPI port operates in full duplex mode,

it supports simultaneous, 16-bit receive (DIN) and transmit (DOUT)

functions during the same data frame.

Figure 26 displays a typical data frame for writing a command to a

control register. In this case, the first bit of the DIN sequence is a

1, followed by a 0, then the 6-bit address and 8-bit data command.

Because each write command covers a single byte of data, two data

frames are required when writing the entire 16-bit space of a register.

Reading the contents of a register requires a modification to the

sequence in Figure 26. In this case, the first two bits in the DIN

sequence are 0, followed by the address of the register. Each register

has two addresses, but either one can be used to access its entire

16 bits of data. The final eight bits of the DIN sequence are irrelevant

and can be counted as don’t cares during a read command. Then,

during the next data frame, the DOUT sequence will contain the

read command requires two separate data frames, the full duplex

mode minimizes this overhead, requiring only one extra data frame

when continuously sampling.

SCLK

DIN

W/R

DC7

DC6

DC5

DC4

DC3

DC2

DC1

DC0

DATA FRAME

WRITE = 1

READ = 0

DATA FOR WRITE COMMANDS

DON’T CARE FOR READ COMMANDS

Figure 26. DIN Bit Sequence

ADDRESS

DON’T CARE

NEXT COMMAND

BASED ON PREVIOUS COMMAND

DATA FRAME

16-BIT REGISTER CONTENTS

SCLK

DIN

DOUT

W/R BIT

ZERO

DATA FRAME

Figure 27. SPI Sequence for Read Commands

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