FastEdge™ Series
CY2DP3110
Document #: 38-07469 Rev.*G
Page 9 of 9
Document History Page
Document Title: CY2DP3110 FastEdge™ Series 1 of 2:10 Differential Clock/Data Fanout Buffer
Document Number: 38-07469
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
121284
11/12/02
RGL
New Data Sheet
*A
126251
04/15/03
RGL
Added VBB in the block diagram
Corrected specs that does not match EROS/IROS
Changed VOHMIN in PECL Output table to VCC-1.2V
Shifted table on ECL levels to match PECL
Added power-up requirements to absolute maximum conditions
Changed title (ComLink to FastEdge)
*B
127696
06/12/03
RGL
Changed operation value from 3.0 GHz to 1.5 GHz in features
Modified Note 21: reduced swing value from up to 3 GHz to 2.2 GHz
*C
128731
08/04/03
RGL
Specified TTB value from TBD to 250 ps
Specified Vo (pp) values from TBDs to 0.34 ps(min) at < 1.5 GHz, 0.30 ps
(typ) at 2.2 GHz
Changed Jitter value from 10 ps to 1 ps (intrinsic)
*D
130299
11/19/03
RGL
Corrected the “VCCO” to “VCC” in the Pin Configuration diagram.
*E
227708
See ECN
RGL/GGK Changed the max. Dissipation, Junction to ambient from 100 to 70°C/W
Added Junction Temperature(TJ) parameter of 150°C max
Replaced ICC calculation with power calculation in the footnote
*F
229393
See ECN
RGL/GGK Provided data for TBD’s to match the device
*G
247626
See ECN
RGL/GGK Changed VOH and VOL to match the Char Data
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