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CY2DP3120AXIT 데이터시트(PDF) 2 Page - Cypress Semiconductor

부품명 CY2DP3120AXIT
상세설명  1:20 Differential Clock/Data Fanout Buffer
PDF  9 Pages
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제조업체  CYPRESS [Cypress Semiconductor]
홈페이지  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY2DP3120AXIT 데이터시트(HTML) 2 Page - Cypress Semiconductor

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FastEdge™ Series
CY2DP3120
Document #: 38-07514 Rev.*C
Page 2 of 9
Governing Agencies
The following agencies provide specifications that apply to the
CY2DP3120. The agency name and relevant specification is
listed below in Table 2.
Pin Definitions[1, 2, 3]
Pin
Name
I/O
Type
Description
3
CLK_SEL I,PD
ECL/PECL/HSTL Input clock select
4
CLKA,
I,PD
ECL/PECL
Differential input clocks
6
VBB[3]
OBias
Reference voltage output
5
CLKA#
I,PD/PU ECL/PECL
Differential input clocks
7
CLKB,
I,PD
HSTL
Alternate differential input clocks
8
CLKB#
I,PD/PU HSTL
Alternate differential input clocks
9
VEE[2]
-PWR
Power
Negative supply
1,2,14,27,40
VCC
+PWR
Power
Positive Supply
52,50,48,46,44,42,39,37,
35,33,31,29,26,24,22,20,
18,16,13,11
Q(0:19)
O
ECL/PECL
True output
51,49,47,45,43,41,38,36,
34,32,30,28,25,23,21,19,
17,15,12,10
Q#(0:19) O
ECL/PECL
Complement output
Table 1.
Control
Operation
CLK_SEL
0
CLKA, CLKA# input pair is active (Default condition with no connection to pin)
CLKA can be driven with ECL- or PECL-compatible signals with respective power configurations
1
CLKB, CLKB# input pair is active.
CLKB can be driven with HSTL-compatible signals with respective power configurations
Table 2.
Agency Name
Specification
JEDEC
JESD 020B (MSL)
JESD 51 (Theta JA)
JESD 8–2 (ECL)
JESD 65–B (skew,jitter)
Mil-Spec
883E Method 1012.1 (Thermal Theta JC)
Notes:
1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power
2. In ECL mode (negative power supply mode), VEE is either –3.3V or –2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode),
VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC)
and are between VCC and VEE.
3. VBB is available for use for single-ended bias mode for |3.3V| supplies (not |2.5V|).



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