8

Am29SL400D

Rev. A Amend. +1 April 13, 2005

ADV ANCE

I N FO RMAT I O N

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state

machine. The state machine outputs dictate the func-

tions, the inputs and control levels they require, and the

resulting output. The following subsections describe

each of these operations in further detail.

Table 1.

Am29SL400D Device Bus Operations

Legend:

Notes:

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the byte or word configura-

tion. If the BYTE# pin is set at logic ‘1’, the device is in

word configuration, DQ15–DQ0 are active and con-

trolled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are

active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must

control and selects the device. OE# is the output

control and gates array data to the output pins. WE#

whether the device outputs array data in words or

bytes.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No

command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that assert

valid addresses on the device address inputs produce

valid data on the device data outputs. The device

remains enabled for read access until the command

register contents are altered.

Operation

CE#

OE# WE# RESET#

Addresses

(Note 1)

DQ0–

DQ7

DQ8–DQ15

BYTE#

BYTE#

Read

L

L

H

H

DQ8–DQ14 = High-Z,

DQ15 = A-1

Write

L

H

L

H

Standby

0.2 V

XX

0.2 V

X

High-Z

High-Z

High-Z

Output Disable

L

H

H

H

X

High-Z

High-Z

High-Z

Reset

X

X

X

L

X

High-Z

High-Z

High-Z

Sector Protect (Note 2)

L

H

L

Sector Address,

A6 = L, A1 = H,

A0 = L

XX

Sector Unprotect (Note 2)

L

H

L

Sector Address,

A6 = H, A1 = H,

A0 = L

XX

Temporary Sector Unprotect

X

X

X

High-Z