AM70PDL129CDH datasheet(83/127 Pages) SPANSION

83 / 127 page

November 24, 2003

Am70PDL127CDH/Am70PDL129CDH

ADV ANCE

I N FO RMAT I O N

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1.

Device Bus Operations

Legend: L = Logic Low = V

IL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,

IN = Address In, DIN = Data In, DOUT = Data Out

Notes:

1. Addresses are A21:A0 in word mode.

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group

Protection and Unprotection” section.

3. If WP# = V

IL, the first or last sector remains protected. If WP# = VIH, the first or last sector will be protected or unprotected as

determined by the method described in “Sector Group Protection and Unprotection”. All sectors are unprotected when shipped

from the factory (The SecSi Sector may be factory protected depending on version ordered.)

4. D

IN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to V

IL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at V

IH.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

data on the device data outputs. The device remains

enabled for read access until the command register

contents are altered.

See “Reading Array Data” for more information. Refer

to the AC Read-Only Operations table for timing speci-

fications and to Figure 14 for the timing diagram. Refer

to the DC Characteristics table for the active current

specification on reading array data.

Operation

CE#

OE#

WE#

RESET#

WP#

ACC

Addresses

(Note 2)

DQ0–

DQ7

DQ8–DQ

Read

AIN

OUT

Write (Program/Erase)

(Note 3)

AIN

(Note 4)

Accelerated Program

(Note 3)

AIN

(Note 4)

Standby

VCC ±

0.3 V

VCC ±

0.3 V

High-Z

Output Disable

High-Z

Reset

High-Z

Sector Group Protect

(Note 2)

VID

SA, A6 =L,

A3=L, A2=L,

A1=H, A0=L

(Note 4)

Sector Group Unprotect

(Note 2)

SA, A6=H,

A3=L, A2=L,

A1=H, A0=L

(Note 4)

Temporary Sector Group

Unprotect

VID

AIN

(Note 4)

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