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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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S71AL016D02 데이터시트(PDF) 72 Page - SPANSION |
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S71AL016D02 데이터시트(HTML) 72 Page - SPANSION |
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72 / 76 page  72 2Mbit Type 2 SRAM SRAM_Type04_04A0 August 4, 2004 Pr e l i m i n a r y Notes: 1. The internal write time of the memory is defined by the overlap of WE#, CE# = VIL, BHE# and/or BLE# = VIL. All signals must be Active to initiate a write, and any of these signals can terminate a write by going Inactive. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 2. Data I/O is high-impedance if OE# = VIH. 3. If CE# goes High simultaneously with WE# High, the output remains in a high-impedance state. 4. During this period, the I/Os are in output state and input signals should not be applied. Figure 5. Write Cycle 1 (WE# Controlled) tHD tSD tPWE tSA tHA tAW tSCE tWC tHZOE DATA IN VALID CE# ADDRESS WE# DATA I/O OE# NOTE 4 tBW BHE#/BLE# |
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