IDT™ / ICS™ SAS/SATA CLOCK GENERATOR

12

ICS843241BG REV. A AUGUST 20, 2008

ICS843241

FEMTOCLOCKS™ SAS/SATA CLOCK GENERATOR

Figure 5 shows an example of ICS843241 application schematic.

In this example, the device is operated at V

CC

= 3.3V. The 18pF

parallel resonant 25MHz crystal is used. The C1 = 27pF and C2

= 27pF are recommended for frequency accuracy. For different

VCC=3.3V

F_SEL0

Set Logic

Input to

'1'

RD1

Not Install

R7

50

(U1-9)

F_SEL1

+

-

Logic Control Input Examples

RU2

Not Install

R3

82.5

C1

27pF

R5

50

To Logic

Input

pins

RU1

1K

Set Logic

Input to

'0'

VCC

VCC

C4

10uF

RD2

1K

X1

25MHz

18pF

U1

ICS843241

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

VEE

XTAL_OUT

XTAL_IN

SSC_SEL0

nc

nc

nc

SSC_SEL1

VCC

F_SEL0

VCC

Q

nQ

nPLL_SEL

VEE

F_SEL1

R2

133

C3

0.1uF

Zo = 50 Ohm

Zo = 50 Ohm

C2

27pF

R1

133

R6

50

VCC

To Logic

Input

pins

VCC

Zo = 50 Ohm

SSC_SEL1

(U1-11)

nPLL_SEL

R4

82.5

SSC_SEL0

Optional

Y-Termination

VCC

(U1-11)

3.3V

+

-

C5

0.1uF

Zo = 50 Ohm

board layout, the C1 and C2 may be slightly adjusted for optimizing

frequency accuracy. Two examples of LVPECL termination are

shown in this schematic. Additional termination approaches are

shown in the LVPECL Termination Application Note.

SCHEMATIC EXAMPLE

FIGURE 5. ICS843241 SCHEMATIC EXAMPLE