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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ICS954321 데이터시트(PDF) 10 Page - Renesas Technology Corp |
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ICS954321 데이터시트(HTML) 10 Page - Renesas Technology Corp |
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10 / 19 page  10 Integrated Circuit Systems, Inc. ICS954321 1078B—09/20/05 SMBus Table: Spread Spectrum Control Register Control Function Bit 7 Reserved Reserved R 0 Bit 6 SSP14 RW X Bit 5 SSP13 RW X Bit 4 SSP12 RW X Bit 3 SSP11 RW X Bit 2 SSP10 RW X Bit 1 SSP9 RW X Bit 0 SSP8 RW X SMBus Table: Output Divider Control Register Control Function Bit 7 SRCCLK Div3 RW 0000:/2 0100:/4 1000:/8 1100:/16 X Bit 6 SRCCLK Div2 RW 0001:/3 0101:/6 1001:/12 1101:/24 X Bit 5 SRCCLK Div1 RW 0010:/5 0110:/10 1010:/20 1110:/40 X Bit 4 SRCCLK Div0 RW 0011:/15 0111:/30 1011:/60 1111:/120 X Bit 3 CPU Div3 RW 0000:/2 0100:/4 1000:/8 1100:/16 X Bit 2 CPU Div2 RW 0001:/3 0101:/6 1001:/12 1101:/24 X Bit 1 CPU Div1 RW 0010:/5 0110:/10 1010:/20 1110:/40 X Bit 0 CPU Div0 RW 0011:/15 0111:/30 1011:/60 1111:/120 X SMBus Table: CLKREQ# Control Register Control Function Bit 7 Reserved Reserved RW 0 Bit 6 SRCCLK4 is controlled RW 1 Bit 5 SRCCLK8 is controlled RW 0 Bit 4 SRCCLK10 is controlled RW 0 Bit 3 Reserved Reserved RW 0 Bit 2 SRCCLK5 is controlled RW 1 Bit 1 SRCCLK7 is controlled RW 0 Bit 0 SRCCLK9 is controlled RW 0 SMBus Table: PLL 2 VCO Frequency Control Register Control Function Bit 7 N Div8 N Divider Prog bit 8 RW X Bit 6 N Div9 N Divider Prog bit 9 RW X Bit 5 M Div5 RW X Bit 4 M Div4 RW X Bit 3 M Div3 RW X Bit 2 M Div2 RW X Bit 1 M Div1 RW X Bit 0 M Div0 RW X SMBus Table: PLL 2 VCO Frequency Control Register Control Function Bit 7 N Div7 RW X Bit 6 N Div6 RW X Bit 5 N Div5 RW X Bit 4 N Div4 RW X Bit 3 N Div3 RW X Bit 2 N Div2 RW X Bit 1 N Div1 RW X Bit 0 N Div0 RW X Not Controlled Controlled 1 The decimal representation of M and N Divier in Byte 17 and 18 will configure the VCO frequency. Default at power up = Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] Controlled 1 Type Not Controlled Controlled Not Controlled -- Controlled - M Divider Programming bits Spread Spectrum Programming b(14:8) 1 CPUDivider Ratio Programming Bits SRCCLK Divider Ratio Programming Bits Type - - - PWD 01 PWD 0 The decimal representation of M and N Divier in Byte 17 and 18 will configure the VCO frequency. Default at power up = Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] PWD Name Type 0 1 PWD PWD Name Type Name 0 - - - - - - - - - - - - Byte 14 Pin # Type - Name OEB# controls selected outputs. Outputs controlled by this pin will be Hi-Z when OEB# is high. OEA# controls selected outputs. Outputs controlled by this pin will be Hi-Z when OEA# is high. - - - - Pin # - Pin # Byte 16 - - Pin # Byte 15 - - - - - - - - Byte 17 Byte 18 - - - Pin # Name - N Divider Programming b(8:0) - - - - - - 0 These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. - Not Controlled Not Controlled Not Controlled - Controlled Controlled |
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