7

COMMERCIALTEMPERATURERANGE

IDT723663/723673 CMOS SyncFIFOTM WITH BUS-MATCHING

4,096 x 36 x 2 and 8,192 x 36 x 2

Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)

0

10

20

3040

5060

70

0

50

100

150

200

250

300

VCC = 5.0V

fS

⎯ Clock Frequency ⎯ MHz

fdata = 1/2 fS

TA = 25oC

CL = 0 pF

VCC = 4.5V

VCC = 5.5V

5610 drw03

80

90

CALCULATING POWER DISSIPATION

The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723663/723673 with CLKA and CLKB

settofS.Alldatainputsanddataoutputschangestateduringeachclockcycletoconsumethehighestsupplycurrent.Dataoutputsweredisconnectedtonormalize

the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of IDT723663/723673 inputs driven by TTL HIGH

levels are known, the power dissipation can be calculated with the equation below.

With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:

PT = VCC x [ICC(f) + (N x

ΔICC x dc)] + Σ(CL x VCC2 X fo)

where:

N

=

number of inputs driven by TTL levels

ΔICC =

increase in power supply current for each input at a TTL HIGH level

dc

=

duty cycle of inputs at a TTL HIGH level of 3.4 V

CL

=

outputcapacitanceload

fo

=

switchingfrequencyofanoutput