12

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM

DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

MARCH 2013

Figure 10. Programmable Full Flag Timing

NOTES:

1. m = PAF offset.

2. (256-m) words for the IDT72801; (512-m) words the IDT72811; (1,024-m) words for the IDT72821; (2,048-m) words for the IDT72831; (4,096-m) words for the IDT72841; or (8,192-m)

words for the IDT72851.

3. tSKEW2 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for PAFA (PAFB) to change during that clock cycle. If the time between the

rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW2, then PAFA (PAFB) may not change state until the next WCLKA (WCLKB) rising edge.

4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in FIFO A (B) when PAFA (PAFB) goes LOW.

tENS

tENH

tENS

tENH

tENS

tENH

WCLKA

(WCLKB)

WENA1

(

WENB1)

WENA2 (WENB2)

(If Applicable)

PAFA

(

PAFB)

RCLKA (RCLKB)

RENA1, RENA2

(

RENB1, RENB2)

(4)

(1)

tPAF

Full - (m+1) words in FIFO

Full - m words in FIFO

(2)

tCLKH

tCLKL

tSKEW2

(3)

tPAF

3034 drw 11

WCLKA (WCLKB)

WENA1

(

WENB1)

WENA2 (WENB2)

(If Applicable)

PAEA,

PAEB

RCLKA (RCLKB)

RENA1, RENA2

(

RENB1, RENB2)

tENS

tENH

tENS

tENH

tSKEW2

(2)

tENS

tENH

tPAE

tPAE

(3)

(1)

n words in FIFO

n+1 words in FIFO

tCLKH

tCLKL

3034 drw 12

NOTES:

1. n = PAE offset.

2. tSKEW2 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for PAEA (PAEB) to change during that clock cycle. If the time between the

rising edge of WCLKA (WCLKB) and the rising edge of RCLKA (RCLKB) is less than tSKEW2, then PAEA (PAEB) may not change state until the next RCLKA (RCLKB) rising edge.

3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in FIFO A (B) when PAEA (PAEB) goes LOW.

Figure 11. Programmable Empty Flag Timing