DSPIC30F datasheet(60/220 Pages) MICROCHIP

60 / 220 page

dsPIC30F5011/5013

DS70116C-page 58

Preliminary

 2004 Microchip Technology Inc.

FIGURE 8-2:

BLOCK DIAGRAM OF A SHARED PORT STRUCTURE

8.2

Configuring Analog Port Pins

The use of the ADPCFG and TRIS registers control the

operation of the A/D port pins. The port pins that are

desired as analog inputs must have their correspond-

ing TRIS bit set (input). If the TRIS bit is cleared

(output), the digital output level (VOH or VOL) will be

converted.

When reading the Port register, all pins configured as

analog input channels will read as cleared (a low level).

Pins configured as digital inputs will not convert an ana-

log input. Analog levels on any pin that is defined as a

digital input (including the ANx pins) may cause the

input buffer to consume current that exceeds the

device specifications.

8.2.1

I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically this instruction

would be a NOP.

EXAMPLE 8-1:

PORT WRITE/READ

EXAMPLE

WR LAT +

TRIS Latch

I/O Pad

WR Port

Data Bus

Data Latch

Read LAT

Read Port

Read TRIS

WR TRIS

Peripheral Output Data

Output Enable

Peripheral Input Data

I/O Cell

Peripheral Module

Peripheral Output Enable

PIO Module

Output Multiplexers

Output Data

Input Data

Peripheral Module Enable

MOV

0xFF00, W0

; Configure PORTB<15:8>

; as inputs

MOV

W0, TRISB

; and PORTB<7:0> as outputs

NOP

; additional instruction

cylcle

btss

PORTB, #13

; bit test RB13 and skip if

set

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