DSPIC30F datasheet(122/220 Pages) MICROCHIP

122 / 220 page

dsPIC30F5011/5013

DS70116C-page 120

Preliminary

 2004 Microchip Technology Inc.

18.3.6

SLAVE FRAME SYNC OPERATION

When the DCI module is operating as a frame sync

slave (COFSD = 1), data transfers are controlled by the

Codec device attached to the DCI module. The

COFSM control bits control how the DCI module

responds to incoming COFS signals.

In the Multi-Channel mode, a new data frame transfer

will begin one CSCK cycle after the COFS pin is sam-

pled high (see Figure 18-2). The pulse on the COFS

pin resets the frame sync generator logic.

In the I2S mode, a new data word will be transferred

one CSCK cycle after a low-to-high or a high-to-low

transition is sampled on the COFS pin. A rising or fall-

ing edge on the COFS pin resets the frame sync

generator logic.

In the AC-Link mode, the tag slot and subsequent data

slots for the next frame will be transferred one CSCK

cycle after the COFS pin is sampled high.

The COFSG and WS bits must be configured to pro-

vide the proper frame length when the module is oper-

ating in the Slave mode. Once a valid frame sync pulse

has been sampled by the module on the COFS pin, an

entire data frame transfer will take place. The module

will not respond to further frame sync pulses until the

data frame transfer has completed.

FIGURE 18-2:

FRAME SYNC TIMING, MULTI-CHANNEL MODE

FIGURE 18-3:

FRAME SYNC TIMING, AC-LINK START OF FRAME

FIGURE 18-4:

I2S INTERFACE FRAME SYNC TIMING

CSCK

CSDI/CSDO

COFS

MSB

LSB

Tag

MSb

BIT_CLK

CSDO or CSDI

SYNC

Tag

bit 14

S12

LSb

S12

bit 1

S12

bit 2

Tag

bit 13

MSB

LSB MSB

LSB

CSCK

CSDI or CSDO

Note:

A 5-bit transfer is shown here for illustration purposes. The I2S protocol does not specify word length - this will

be system dependent.

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