COMMERCIALTEMPERATURERANGE

IDTCV115F

PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR

13

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

VIH

Input HIGH Voltage

3.3V ± 5%

2

—

VDD + 0.3

V

VIL

Input LOW Voltage

3.3V ± 5%

VSS - 0.3

—

0.8

V

VIH_FS

FS Input HIGH Voltage

For FSA,B,C and Test_Mode

0.7

—

VDD + 0.3

V

VIL_FS

FS Input LOW Voltage

For FSA,B,C and Test_Mode

VSS - 0.3

—

0.35

V

IIL

Input LeakageCurrent

0< VIN < VDD, no internal pull-up or pull-down

–5

—

+5

μA

IDD3.3OP

Operating Supply Current

Full active, CL = full load

—

—

400

mA

IDD3.3PD

Powerdown Current

All differential pairs driven

—

—

70

mA

All differential pairs tri-stated

—

—

12

FI

Input Frequency(1)

VDD = 3.3V

—

14.31818

—

MHz

LPIN

Pin Inductance(2)

——

7

nH

CIN

Logic inputs

—

—

5

COUT

Input Capacitance(2)

Output pin capacitance

—

—

6

pF

CINX

XTAL_IN and XTAL_OUT pins

—

—

5

TSTAB

Clock Stabilization(2,3)

From VDD power-up or de-assertion of PD# to first clock

—

—

1.8

ms

Modulation Frequency(2)

Triangular modulation

30

—

33

KHz

TDRIVE_SRC(2)

SRC output enable after PCI_Stop# de-assertion

—

—

15

ns

TDRIVE_PD#(2)

CPU output enable after PD# de-assertion

—

—

300

us

TFALL_PD#(2)

Fall time of PD#

—

—

5

ns

TRISE_PD#(2)

Rise time of PD#

—

—

5

ns

TDRIVE_CPU_Stop#(2)

CPU output enable after CPU_Stop# de-assertion

—

—

10

us

TFALL_CPU_Stop#(2)

Fall time of PD#

—

—

5

ns

TRISE_CPU_Stop#(2)

Rise time of PD#

—

—

5

ns

ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT

PARAMETERS

Following Conditions Apply Unless Otherwise Specified:

Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%

NOTES:

1.

Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.

2.

This parameter is guaranteed by design, but not 100% production tested.

3.

See TIMING DIAGRAMS for timing requirements.