S29PL-J55BAI011 datasheet(4/96 Pages) SPANSION

4 / 96 page

S29PL-J

S29PL-J_00_A9 September 22, 2006

Data

Sheet

(Adv an ce

Inf o r m a t io n)

General Description

The PL127J/PL129J/PL064J/PL032J is a 128/128/64/32 Mbit, 3.0 volt-only Page Mode and Simultaneous

Read/Write Flash memory device organized as 8/8/4/2 Mwords. The devices are offered in the following

packages:

– 11 mm x 8 mm, 80-ball Fine-pitch BGA standalone (PL127J)

– 8 mm x 11.6 mm, 64-ball Fine-pitch BGA multi-chip compatible (PL127J)

– 8.15 mm x 6.15 mm, 48-ball Fine-pitch BGA standalone (PL064J/PL032J)

– 7 mm x 9 mm, 56-ball Fine-pitch BGA multi-chip compatible (PL064J and PL032J)

– 20 mm x 14 mm, 56-pin TSOP (PL127J)

The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or in standard

EPROM programmers. A 12.0 V VPP is not required for write or erase operations.

The device offers fast page access times of 20 to 30 ns, with corresponding random access times of 55 to

70 ns, respectively, allowing high speed microprocessors to operate without wait states. To eliminate bus

contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

Note: Device PL129J has 2 chip enable inputs (CE1#, CE2#).

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