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HD74LS112P 데이터시트(PDF) 6 Page - Renesas Technology Corp

부품명 HD74LS112P
상세설명  Dual J-K Negative-edge-triggered Flip-Flops (with Preset and Clear)
PDF  11 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD74LS112P 데이터시트(HTML) 6 Page - Renesas Technology Corp

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HD74LS112
Rev.3.00, Jul.13.2005, page 4 of 8
Timing Definition
J, K
Clock
0 V
3 V
0 V
3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
"H" Data
"L" Data
tw
tsu
th
tsu
th
Testing Method
Test Circuit
1.
ƒ
max, tPLH, tPHL, (Clock
→Q, Q)
PR
4.5V
VCC
CK
Output Q
Output
Q
Input
J
K
Q
Q
CLR
P.G.
Zout=50
Ω
Same as Load Circuit 1.
RL
Load circuit 1
CL
Notes:
1.
Test is put into the each flip-flop.
2.
CL includes probe and jig capacitance.
3.
All diodes are 1S2074(H).



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