MPC9817 REVISION 3 AUGUST 16, 2012

2

©2012 Integrated Device Technology, Inc.

MPC9817 Data Sheet

CLOCK GENERATOR FOR POWERQUICC AND POWERPC MICROPROCESSORS AND MICROCONTROLLERS

Figure 1. MPC9817 Logic Diagram

Table 1. Pin Configurations

Pin

I/O

Type

Function

QA0, QA1, QA2, QA3, QA4

Output

LVCMOS

Clock Outputs

QREF0, QREF1, QREF2

Output

LVCMOS

Reference Output (25 MHz)

XTAL_IN

Input

LVCMOS

Crystal Oscillator Input Pin

XTAL_OUT

Output

LVCMOS

Crystal Oscillator Output Pin

FSEL0, FSEL1

Input

LVCMOS

Configures Bank A Clock Output Frequency (pull-up)

MR/OE

Input

LVCMOS

Enables All Outputs (pull-down)

VDD

—

—

3.3-V Supply

GND

—

—

Ground

Table 2. Function Table

Control

Default

00

01

10

11

FSEL0,FSEL1

11

25 MHz fed directly

from reference input,

PLL disabled

33 MHz

50 MHz

66 MHz

Ref

PLL

400 MHz

QA0

QA1

QA2

QA4

XTAL_IN

OSC

XTAL_OUT

FSEL0

QREF0

FSEL1

QA3

QREF1

QREF2

Data

Generator

MR/OE

33,50,66 MHz

25 MHz