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VL-FS-MDLS16166D-01 데이터시트(PDF) 9 Page - Varitronix international limited |
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VL-FS-MDLS16166D-01 데이터시트(HTML) 9 Page - Varitronix international limited |
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9 / 12 page ![]() VL-FS-MDLS16166D-01 REV. A (MDLS16166(33)-LV-G-LED01G (DIE FORM IC)) JAN./2002 PAGE 9 OF 12 4.3 Timing Specifications At Ta = 0 °C To +50 °C , VDD = +5V±5%, VSS = 0V. Refer to Fig. 2, the bus timing diagram for write mode. Table 6 Parameter Symbol Min. Max. Unit Remarks Enable cycle time tCYCE 500 - ns Enable ”High” level pulse width tWHE 300 - ns Enable rise time tRE - 25 ns Enable fall time tFE - 25 ns 60 - ns 8-bit operation mode RS, R/W set-up time tAS 100 4-bit operation mode RS, R/W address hold time tAH 10 - ns Data output delay tDS 100 - ns Data hold time tDHR 10 - ns Refer to Fig. 3, the bus timing diagram for read mode . Table 7 Parameter Symbol Min. Max. Unit Remarks Enable cycle time tCYCE 500 - ns Enable ”High” level pulse width tWHE 300 - ns Enable rise time tRE - 25 ns Enable fall time tFE - 25 ns 60 - ns 8-bit operation mode RS, R/W set-up time tAS 100 4-bit operation mode RS, R/W address hold time tAH 10 - ns Read data output delay tRD - 190 ns Read data hold time tDHR 20 - ns |
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