ADG841/ADG842

Rev. 0 | Page 13 of 16

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-203-AB

0.22

0.08

0.30

0.10

0.30

0.15

1.00

0.90

0.70

SEATING

PLANE

4

5

6

3

2

1

PIN 1

0.65 BSC

1.30 BSC

0.10 MAX

0.10 COPLANARITY

0.40

0.10

1.10

0.80

2.20

2.00

1.80

2.40

2.10

1.80

1.35

1.25

1.15

Figure 25. 6-Lead Thin Shrink Small Outline Transistor [SC70]

(KS-6)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

Branding1

ADG841YKSZ-500RL72

–40°C to +125°C

6-Lead Thin Shrink Small Outline Transistor (SC70)

KS-6

SVA

ADG841YKSZ-REEL2

–40°C to +125°C

6-Lead Thin Shrink Small Outline Transistor (SC70)

KS-6

SVA

ADG841YKSZ-REEL72

–40°C to +125°C

6-Lead Thin Shrink Small Outline Transistor (SC70)

KS-6

SVA

ADG842YKSZ-500RL72

–40°C to +125°C

6-Lead Thin Shrink Small Outline Transistor (SC70)

KS-6

SWA

ADG842YKSZ-REEL2

–40°C to +125°C

6-Lead Thin Shrink Small Outline Transistor (SC70)

KS-6

SWA

ADG842YKSZ-REEL2

–40°C to +125°C

6-Lead Thin Shrink Small Outline Transistor (SC70)

KS-6

SWA