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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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CYT2CL 데이터시트(PDF) 39 Page - Infineon Technologies AG |
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CYT2CL 데이터시트(HTML) 39 Page - Infineon Technologies AG |
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39 / 174 page  12 Power pin assignments Table 12-1 Power pin assignments Name Package Remarks 176-LQFP 144-LQFP VDDD 105, 104, 88, 66, 45, 20 85, 84, 72, 54, 37, 20 Main digital supply VSS 133, 107, 99, 89, 67, 44, 22 109, 87, 79, 73, 55, 36, 22 Main digital ground VDDIO_GPIO 132 108 Supply for GPIO_STD (2.7 - 5.5 V) VDDIO_HSIO 176, 18, 13, 7 144, 18, 13, 7 Supply for HSIO_STDLN (3.0 - 3.6 V) VSSIO_HSIO 19, 12, 6, 1 19, 12, 6, 1 HSIO_STDLN ground VDDIO_SMC 174, 164, 155, 145 142, 132, 123, 113 Supply for GPIO_SMC (2.7 - 5.5 V) VSSIO_SMC 175, 165, 154, 144 143, 133, 122, 112 GPIO_SMC ground VCCD[24] 106, 21 86, 21 Main regulated supply. Driven by LDO regulator VREFH 129 105 High reference voltage for SAR VDDA_ADC 130 106 Main analog supply (for PASS/SAR) VSSA_ADC 131 107 Main analog ground (VREFL is shared with VSSA_ADC) XRES_L 108 88 Active low external reset input Note 24.The VCCD pins must be connected together to ensure a low-impedance connection. (see the requirement in Figure 27-2) |
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