Nexperia

74LVC377

Octal D-type flip-flop with data enable; positive-edge trigger

-40 °C to +85 °C

-40 °C to +125 °C

Symbol Parameter

Conditions

Min

Typ [1] Max

Min

Max

Unit

per flip-flop; VI = GND to VCC

[4]

VCC = 1.65 V to 1.95 V

-

12.1

-

-

-

pF

VCC = 2.3 V to 2.7 V

-

15.8

-

-

-

pF

CPD

power dissipation

capacitance

VCC = 3.0 V to 3.6 V

-

19.0

-

-

-

pF

[1] Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.

[2] tpd is the same as tPLH and tPHL.

[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[4] CPD is used to determine the dynamic power dissipation (PD in μW).

PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where:

fi = input frequency in MHz; fo = output frequency in MHz

CL = output load capacitance in pF

VCC = supply voltage in Volts

N = number of inputs switching

Σ(CL × VCC 2 × fo) = sum of the outputs

10.1. Waveforms and test circuit

mna894

CP input

Qn output

tPHL

tPLH

tW

1/fmax

VM

VOH

VI

GND

VOL

VM

Measurement points are given in Table 8.

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.

Fig. 4. Propagation delay clock (CP) to output (Qn), pulse width clock (CP), and maximum frequency

th

tsu

th

tsu

VM

VM

GND

VCC

GND

VCC

Dn input

tsu

tW

VM

mna921

GND

VCC

CP input

E input

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 5. Data set-up and hold times of data input (Dn) and enable input (E) and pulse width of enable input (E)

74LVC377

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 7 — 27 August 2021

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