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ADN2817 데이터시트(PDF) 26 Page - Analog Devices

부품명 ADN2817
상세설명  Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery ICs
PDF  35 Pages
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ADN2817 데이터시트(HTML) 26 Page - Analog Devices

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ADN2817/ADN2818
Preliminary Technical Data
Rev. PrA | Page 26 of 35
completely bypassing the CDR.
DISABLE OUTPUT BUFFERS
The ADN2817/18 provides the option of disabling the output
buffers for power savings. The clock output buffers can be
disabled by setting CTRLD[5]=1. For additional power savings,
e.g. in a low power standby mode, the data output buffers can
also be disabled by setting CTRLD[6]=1.



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