NB6L14M datasheet(2/11 Pages) ONSEMI

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NB6L14M

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VCC

VREFAC

Exposed Pad (EP)

Figure 2. QFN−16 Pinout

(Top View)

GND

Figure 3. Logic Diagram

/Q0

/Q1

/Q2

/Q3

50 W

/IN

VREFAC

CLK

Table 1. EN TRUTH TABLE

Q0:Q3

+ = On next negative transition of the input signal (IN).

x = Don’t care.

Table 2. PIN DESCRIPTION

Name

I/O

Description

CML Output

Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.

CML Output

Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC .

CML Output

Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.

CML Output

Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.

CML Output

Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.

CML Output

Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.

VCC

−

Positive Supply Voltage

LVTTL/LVCMOS

Synchronous Output Enable. When LOW, Q outputs will go LOW and Q outputs will

go HIGH on the next negative transition of IN input. The internal DFF register is

clocked on the falling edge of IN input (see Figure 16). The EN pin has an internal

pullup resistor and defaults HIGH when left open.

CML, CML, LVDS,

HSTL

Inverted Differential Clock Input. Internal 50 W Resistor to Termination Pin, VT.

VREFAC

Output Voltage Reference for capacitor−coupled inputs, only.

Internal 100 W center−tapped Termination Pin for IN and IN.

CML, CML, LVDS,

HSTL

Non−inverted Differential Clock Input. Internal 50 W Resistor to Termination Pin, VT.

GND

−

Negative Supply Voltage

VCC

−

Positive Supply Voltage

CML Output

Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC.

CML Output

Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.

−

The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the

die for improved heat transfer out of package. The exposed pad must be attached to

a heat−sinking conduit. The pad is not electrically connected to the die, but is

recommended to be electrically and thermally connected to GND on the PC board.

1. In the differential configuration when the input termination pin VT, is connected to a common termination voltage or left open, and if no signal

is applied on IN/IN inputs, then the device will be susceptible to self−oscillation.

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