| 전자부품 데이터시트 검색엔진 |
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74LVC74AD 데이터시트(PDF) 9 Page - Nexperia B.V. All rights reserved |
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74LVC74AD 데이터시트(HTML) 9 Page - Nexperia B.V. All rights reserved |
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9 / 16 page ![]() Nexperia 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger mna423 trec tPHL tPHL tW tPLH tPLH VM VM VM tW VM VM VI GND VI GND nSD input VI GND nRD input nCP input VOH VOL nQ output VOH VOL nQ output Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 8. The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths, and the nRD to nCP recovery time Table 9. Measurement points Supply voltage Input Output VCC VI VM VM 1.2 V VCC 0.5 x VCC 0.5 x VCC 1.65 V to 1.95 V VCC 0.5 x VCC 0.5 x VCC 2.3 V to 2.7 V VCC 0.5 x VCC 0.5 x VCC 2.7 V 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V 74LVC74A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 9 — 20 August 2021 9 / 16 |
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