Nexperia

74LVC74A

Dual D-type flip-flop with set and reset; positive-edge trigger

5. Pinning information

5.1. Pinning

74LVC74A

1RD

VCC

1D

2RD

1CP

2D

1SD

2CP

1Q

2SD

1Q

2Q

GND

2Q

001aad106

1

2

3

4

5

6

7

8

10

9

12

11

14

13

Fig. 5. Pin configuration SOT108-1 (SO14) and

SOT402-1 (TSSOP14)

001aad107

74LVC74A

Transparent top view

1Q

2Q

1Q

2SD

1SD

2CP

1CP

2D

2RD

1D

GND(1)

6

9

5

10

4

11

3

12

2

13

terminal 1

index area

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND.

Fig. 6. Pin configuration for SOT762-1 (DHVQFN14)

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

1RD

1

asynchronous reset-direct input (active LOW)

1D

2

data input

1CP

3

clock input (LOW-to-HIGH, edge-triggered)

1SD

4

asynchronous set-direct input (active LOW)

1Q

5

true output

1Q

6

complement output

GND

7

ground (0 V)

2Q

8

complement output

2Q

9

true output

2SD

10

asynchronous set-direct input (active LOW)

2CP

11

clock input (LOW-to-HIGH, edge-triggered)

2D

12

data input

2RD

13

asynchronous reset-direct input (active LOW)

VCC

14

supply voltage

74LVC74A

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 9 — 20 August 2021

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