Nexperia

74LVC3G34

Triple buffer

11.1. Waveforms and test circuit

mnb072

nA input

nY output

tPLH

tPHL

GND

VI

VM

VM

VM

VM

VOH

VOL

Measurement points are given in Table 9.

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.

Fig. 6. The data input (nA) to output (nY) propagation delays

Table 9. Measurement points

Supply voltage

Input

Output

VCC

VM

VM

1.65 V to 1.95 V

0.5 × VCC

0.5 × VCC

2.3 V to 2.7 V

0.5 × VCC

0.5 × VCC

2.7 V

1.5 V

1.5 V

3.0 V to 3.6 V

1.5 V

1.5 V

4.5 V to 5.5 V

0.5 × VCC

0.5 × VCC

VEXT

VCC

VI

VO

mna616

DUT

CL

RT

RL

RL

G

Test data is given in Table 10.

Definitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Fig. 7. Test circuit for measuring switching times

Table 10. Test data

Supply voltage

Input

Load

VEXT

VCC

VI

tr = tf

CL

RL

tPLH, tPHL

1.65 V to 1.95 V

VCC

≤ 2.0 ns

30 pF

1 kΩ

open

2.3 V to 2.7 V

VCC

≤ 2.0 ns

30 pF

500 Ω

open

2.7 V

2.7 V

≤ 2.5 ns

50 pF

500 Ω

open

3.0 V to 3.6 V

2.7 V

≤ 2.5 ns

50 pF

500 Ω

open

4.5 V to 5.5 V

VCC

≤ 2.5 ns

50 pF

500 Ω

open

74LVC3G34

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 14 — 25 August 2021

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