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AD15452/PCB 데이터시트(PDF) 3 Page - Analog Devices

부품명 AD15452/PCB
상세설명  12-Bit 65 MSPS Quad A/D Converter with Integrated Signal Conditioning
PDF  16 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD15452/PCB 데이터시트(HTML) 3 Page - Analog Devices

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AD15452
Rev. 0 | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
@ AVDD = DRVDD = PLLVDD = 3.3 V, Encode = 65 MSPS, AIN = −9 dBFS differential input, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Temp
Test Level
Min
Typ
Max
Unit
RESOLUTION
12
Bits
ACCURACY
No Missing Codes
Full
IV
Guaranteed
Offset Error
25°C
I
−5
+5
% FSR
Gain Error
25°C
I
−12.5
+12.5
% FSR
Differential Nonlinearity (DNL)
Full
V
±0.35
LSB
Integral Nonlinearity (INL)
Full
V
±0.5
LSB
TEMPERATURE DRIFT
Offset Error
Full
V
±10
ppm/oC
Gain Error
Full
V
±290
ppm/oC
MATCHING CHARACTERISTICS
Offset Error
Full
V
±2
% FSR
Gain Error
Full
V
±1.2
% FSR
INPUT REFERRED NOISE
Full
V
0.82
LSB rms
ANALOG INPUT
Input Range
Full
IV
296
mV p-p
Input Resistance1
25°C
V
100
Ω
Input Capacitance1
25°C
V
2.5
pF
CLOCK INPUTS
High Level Input Voltage (VIH)
Full
IV
2
V
Low Level Input Voltage (VIL)
Full
IV
0.8
V
High Level Input Current (IIH)
Full
IV
−10
+10
μA
Low Level Input Current (IIL)
Full
IV
−10
+10
μA
Input Capacitance (CIN)
Full
V
2
pF
POWER-DOWN INPUT
Logic 1 Voltage
Full
IV
2
V
Logic 0 Voltage
Full
IV
0.8
V
Input Capacitance
Full
V
2
pF
DIGITAL OUTPUTS (LVDS)
Differential Output Voltage (VOD)
Full
VI
260
440
mV
Output Offset Voltage (VOS)
Full
VI
1.15
1.35
V
Output Coding
Offset binary
CLOCK
Maximum Conversion Rate
Full
VI
65
MSPS
Minimum Conversion Rate
Full
IV
10
MSPS
Clock Pulse Width High (tEH)
Full
VI
6.2
ns
Clock Pulse Width Low (tEL)
Full
VI
6.2
ns
OUTPUT PARAMETERS
Propagation Delay (tpd)
Full
VI
3.3
6.5
7.9
ns
Rise Time (tR)2
Full
V
250
ps
Fall Time (tF)2
Full
V
250
ps
FCO Propagation Delay (tFCO)
Full
V
6.5
ns
DCO Propagation Delay (tDCO)
Full
V
tFCO + tSAMPLE/24
ns
DCO to Data Delay (tDATA)
Full
IV
tSAMPLE/24 − 250
tSAMPLE/24
tSAMPLE/24 + 250
ps
DCO − FCO Delay (tFRAME)
Full
IV
tSAMPLE/24 − 250
tSAMPLE/24
tSAMPLE/24 + 250
ps
Data to Data Skew
Full
IV
±100
±250
ps
Wake-Up Time
25°C
V
250
ns
Pipeline Latency
Full
IV
10
Cycles



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