Preliminary Technical Data

AD7631/AD7634

Rev. PrC | Page 7 of 14

Parameter

Symbol

Min

Typ

Max

Unit

BUSY High in Master Serial Read after Convert4

See

Table 4

CNVST Low to SYNC Asserted Delay (all Modes)

ns

AD7631

TBD

ns

AD7634 (Warp Mode/Normal Mode/Impulse Mode)

TBD

ns

SYNC Deasserted to BUSY Low Delay

25

ns

SLAVE SERIAL INTERFACE MODES

External SCLK Setup Time

5

ns

External SCLK Active Edge to SDOUT Delay

1

8

ns

SDIN Setup Time

5

ns

SDIN Hold Time

5

ns

External SCLK Period

12.5

ns

External SCLK High

5

ns

External SCLK Low

5

ns

Table 4. Serial Clock Timings in Master Read After Convert Mode

DIVSCLK[1]

0

0

1

1

DIVSCLK[0]

Symbol

0

1

0

1

Unit

SYNC to SCLK First Edge Delay Minimum

3

17

17

17

ns

Internal SCLK Period Minimum

25

60

120

240

ns

Internal SCLK Period Maximum

40

80

160

320

ns

Internal SCLK High Minimum

12

22

50

100

ns

Internal SCLK Low Minimum

7

21

49

99

ns

SDOUT Valid Setup Time Minimum

4

18

18

18

ns

SDOUT Valid Hold Time Minimum

2

4

30

89

ns

SCLK Last Edge to SYNC Delay Minimum

3

60

140

300

ns

BUSY High Width Maximum (Warp mode)

1.75

2.5

4

7

μs

BUSY High Width Maximum (Normal mode)

2

2.75

4.25

7.25

μs

BUSY High Width Maximum (Impulse mode)

2.25

3

4.5

7.5

μs