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BSP255 데이터시트(PDF) 7 Page - NXP Semiconductors |
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BSP255 데이터시트(HTML) 7 Page - NXP Semiconductors |
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7 / 10 page ![]() 1996 Aug 05 7 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSP255 Fig.9 Drain source on-state resistance as a function of gate-source voltage; typical values. VDS ≥ ID × RDSon; Tj =25 °C. (1) ID = −10 mA. (2) ID = −50 mA. (3) ID = −80 mA. (4) ID = −160 mA. (5) ID = −325 mA. handbook, halfpage −10 VGS (V) 0 MBH437 102 10 −2 −4 −6 RDSon ( Ω) −8 (1) (2) (3) (4) (5) Fig.10 Capacitance as a function of drain-source voltage; typical values. VGS = 0; f = 1 MHz; Tj =25 °C. handbook, halfpage 0 120 160 80 40 0 −10 −20 −50 −40 −30 MBH442 C (pF) VDS (V) Crss Ciss Coss Fig.11 Switching time test circuit and input and output waveforms. handbook, full pagewidth MGD391 10 % 90 % Vin Vout td(on) ton toff tr tf td(off) 10 % 90 % 10 % 90 % 0 0 −VDD RL Vout Vin |
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