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4LS

Functional Description

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 33

7.9

Training Sequence / Pattern

The use of a Training Sequence/Pattern is implemented on the sensor so that the FPGA can

synchronize the receiver for the optimal centered clock edge. The period of each bit is given by the

PLL Clock Period, as shown in Figure 42, for the respective MCLK values.

The Training Sequence (TS) is defined by the use of three registers. The tables below gives a

representation of the three registers combined together to form the training sequence.

Figure 44:

Transmission of Training Sequence with 8-Bit Resolution

Word

TSA

TSB

Bit

Training Sequence 1

Training Sequence 3

Training Sequence 2

Training Sequence 3

Figure 45:

Transmission of Training Sequence with 12-Bit Resolution

Word

TSA

TSB

Bit

…

Training Sequence 1

Training Sequence 3

Training Sequence 2

Training Sequence 3

…

Figure 46 presents the transmission for the training pattern over the time, in relation to the LVAL

signal. As soon as the sensor is powered (respecting power-on-sequence), starts transmitting the

Training Sequence. The TS is always transmitted before the Valid Training Sequence (VTS) and when

the FPGA no longer requests for readout. The VTS has the same value as TS but is comprehended

between the falling edge of START_READOUT and following LVAL rising edge signals, as

represented on Figure 52 and Figure 53.

Figure 46:

Training Pattern Transmission

Pending on the transmission mode (12-bit or 8-bit at 4-To-1, 2-To-1 or 1-To-1), the VTS number of

words or clocks (each clock is equal to TMCLK) varies, as shown below. Please note that Word B is

always the first word after the START_READOUT falling edge.

Start_Readout

LVAL

Data

VTS

Line Data

VTS

Line Data

VTS

Line Data

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