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4LS

Functional Description

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 24

Status 4

Bit 4

Status 4

Bit 3

Test Mode

Bit 0

Operation Mode Selected

Remark

ADC Test Mode

Internal Use Only

Do Not Use.

To operate in standard mode it is necessary to act in:

●

RST_CVC_L1 and RST_CVC_L2

●

RST_CDS_L1 and RST_CDS_L2

●

SAMPLE_L1 and SAMPLE_L2

●

Select CVC (Full Well Capacitance is configurable) and CDS gain using registers.

The next figure exemplifies how to act in these signals during this operation mode. For more details,

please refer to section 7.11.

Figure 31:

Standard Mode Operation

The sensor features a 12-bit ADC with programmable conversion gain and end range. The on chip

digital control circuit generates all necessary control signals for conversion and the readout modes.

The start of conversion and start of readout for a new line can optionally be triggered by external

signals. The ADC conversion range can be programmed over the serial interface. Higher conversion

range requires longer ADC conversion time.

"Companding" A/D conversion is presented with a total of four A/D conversion gains, each doubling

the conversion step for the next higher signal range. The thresholds for the doubling of the conversion

step are programmable over the serial configuration interface.

The sensor enables interleaved integration, A/D conversion and readout, therefore the overall pipeline

delay is minimum two line times.

RST_CVC_Lx

RST_CDS_Lx

Integration

Sample_Lx

Integration

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