AD9510SLASHPCB datasheet(51/60 Pages) AD

51 / 60 page

AD9510

Rev. A | Page 51 of 60

Reg.

Addr.

(Hex) Bit(s) Name

Description

<4:2> Prescaler Value

(P/P+1)

<4>

<3>

<2>

Mode

Prescaler Mode

Divide by 1

Divide by 2

2/3

4/5

8/9

16/17

32/33

Divide by 3

DM = Dual Modulus, FD = Fixed Divide.

<5>

Not Used

<6>

B Counter Bypass

Only valid when operating the prescaler in fixed divide (FD) mode. When this bit is set, the B counter is

divided by 1. This allows the prescaler setting to determine the divide for the N divider.

<7>

Not Used

<5:0> 14-Bit Reference

Counter, MSBs

R Divider (MSB) <13:8>

<7:0> 14-Bit Reference

Counter, R LSBs

R Divider (MSB) <7:0>

<1:0> Antibacklash Pulse

Width

<1>

<0>

Antibacklash Pulse Width (ns)

1.3 (Default)

2.9

6.0

1.3

<4:2>

Not Used

<5>

Digital Lock Detect

Window

<5>

Digital Lock Detect Window (ns)

Digital Lock Detect Loss-of-Lock Threshold (ns)

0 (Default)

9.5

3.5

Digital Lock Detect

Window

If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window

time, the digital lock detect flag is set. The flag remains set until the time difference is greater than the

loss-of-lock threshold.

<6>

Lock Detect

Disable

0 = Normal Lock Detect Operation (Default)

1 = Disable Lock Detect

<7>

Not Used

Unused

0E-33

Not Used

Fine Delay Adjust

<0>

Delay Control

Delay Block Control Bit

OUT5

Bypasses Delay Block and Powers It Down (Default = 1b)

(38)

(OUT6)

<7:1>

Not Used

(38)

<2:0> Ramp Current

OUT5

The slowest ramp (200 μA) sets the longest full scale of approximately 10 ns.

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