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28F640L30 데이터시트(PDF) 21 Page - Intel Corporation

부품명 28F640L30
상세설명  1.8 Volt Intel StrataFlash짰 Wireless Memory with 3.0-Volt I/O (L30)
PDF  100 Pages
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제조업체  INTEL [Intel Corporation]
홈페이지  http://www.intel.com
Logo INTEL - Intel Corporation

28F640L30 데이터시트(HTML) 21 Page - Intel Corporation

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28F640L30, 28F128L30, 28F256L30
Datasheet
21
Block
Locking/
Unlocking
0x60
Lock Block
Setup
First cycle of a 2-cycle command; prepares the CUI for block lock configuration changes. If the
next command is not Block Lock (0x01), Block Unlock (0xD0), or Block Lock-Down (0x2F), the
CUI sets Status Register bits SR[4] and SR[5], indicating a command sequence error.
0x01 Lock Block
If the previous command was Block Lock Setup (0x60), the addressed block is locked.
0xD0 Unlock Block
If the previous command was Block Lock Setup (0x60), the addressed block is unlocked. If the
addressed block is in a lock-down state, the operation has no effect.
0x2F
Lock-Down
Block
If the previous command was Block Lock Setup (0x60), the addressed block is locked down.
Protection 0xC0
Program
Protection
Register
Setup
First cycle of a 2-cycle command; prepares the device for a Protection Register or Lock
Register program operation. The second cycle latches the register address and data, and starts
the programming algorithm
Configu-
ration
0x60
Read
Configuration
Register
Setup
First cycle of a 2-cycle command; prepares the CUI for device read configuration. If the Set
Read Configuration Register command (0x03) is not the next command, the CUI sets Status
Register bits SR[4] and SR[5], indicating a command sequence error.
0x03
Read
Configuration
Register
If the previous command was Read Configuration Register Setup (0x60), the CUI latches the
address and writes A[15:0] to the Read Configuration Register. Following a Configure Read
Configuration Register command, subsequent read operations access array data.
Table 6.
Command Codes and Definitions (Sheet 2 of 2)
Mode
Code Device Mode
Description



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