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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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WM8985 데이터시트(PDF) 73 Page - Wolfson Microelectronics plc |
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WM8985 데이터시트(HTML) 73 Page - Wolfson Microelectronics plc |
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73 / 118 page  Pre-Production WM8985 w PP, Rev 3.4, October 2006 73 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R49 (31h) 0 VROI 0 VREF (AVDD1/2) to analogue output resistance 0 = approx 1k Ω 1 = approx 30 k Ω Table 41 Disabled Outputs to VREF Resistance A dedicated buffer is available for biasing unused analogue I/O pins as shown in Figure 30. This buffer can be enabled using the BUFIOEN register bit. Figure 30 summarises the bias options for the output pins. AVDD/2 - + AVDD/2 Used to tie off all unused inputs and outputs BUFIOEN R1[2] Analogue inputs LOUT2 ROUT2 OUT3 1k 30k VROI R49[0] 1k 30k VROI R49[0] 1k 30k VROI R49[0] OUT4 1k 30k VROI R49[0] LOUT1 1k 30k VROI R49[0] ROUT1 1k 30k VROI R49[0] Figure 30 Unused Input/Output Pin Tie-off Buffers L/ROUT2EN/ OUT3/4EN VROI OUTPUT CONFIGURATION 0 0 1kΩ to AVDD1/2 0 1 30kΩ to AVDD1/2 1 X Output enabled (DC level=AVDD1/2) Table 42 Unused Output Pin Bias Options |
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