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INA780B 데이터시트(PDF) 32 Page - Texas Instruments |
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INA780B 데이터시트(HTML) 32 Page - Texas Instruments |
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32 / 42 page ![]() 8.4.2 Layout Example 2 Address Lines A1, A0 via to connect directly to VS, GND, SDA, or SCL to set device address Device Bypass Capcitor I2C bus connections for clock and data (pullup resistors not shown) TI Device IS+ IS Place vias connecting to inner or bottom layers as close as possible to the device. The number of vias required depends on operational current and ambient conditions (1) All vias close to the pin pads should be tented. (2) All Vias are either 8 mil/18 mil or 15 mil/25 mil with a 5 mill annular ring. (3) The distance between the IS+ and IS- power pours is 8 mil. Figure 8-3. INA780x Layout Example INA780A, INA780B SBOSAB6 – JULY 2023 www.ti.com 32 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: INA780A INA780B |
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