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CS4350 데이터시트(PDF) 14 Page - Cirrus Logic

부품명 CS4350
상세설명  192 kHz Stereo DAC with Integrated PLL
PDF  39 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS4350 데이터시트(HTML) 14 Page - Cirrus Logic

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14
DS691A3
CS4350
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, CL =20pF)
Notes:
9.
tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
10. Data must be held for sufficient time to bridge the transition time of CCLK.
11. For FSCK < 1 MHz.
12. CDOUT should not be sampled during this time.
Figure 6. Control Port Timing - SPI Mode
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
fsclk
-6
MHz
RST Rising Edge to CS Falling
tsrs
500
-
ns
CCLK Edge to CS Falling (Note 9)
tspi
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
µs
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time (Note 10)
tdh
15
-
ns
Rise Time of CCLK and CDIN (Note 11)
tr2
-
100
ns
Fall Time of CCLK and CDIN (Note 11)
tf2
-
100
ns
Transition Time from CCLK to CDOUT Valid (Note 12)
tr2
-
100
ns
Time from CS rising to CDOUT High-Z
tf2
-
100
ns
t r2
t f2
t dsu t dh
t sch
t scl
CS
CCLK
CDIN
t css
t csh
t spi
t srs
RST
CDOUT
t
scdov
t
scdov
t cscdo
Hi-Im pedance



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