Nexperia

74HC191

Presettable synchronous 4-bit binary up/down counter

aaa-024390

VM

GND

Dn input

GND

th

PL input

VM

tsu

tsu

th

Vl

Vl

Measurement points are given in Table 9.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 17. The parallel load input (PL) to data input (Dn) set-up and hold times

Table 9. Measurement points

Input

Output

VM

VI

VM

0.5 x VCC

GND to VCC

0.5 x VCC

VM

VM

tW

tW

10 %

90 %

0 V

VI

VI

negative

pulse

positive

pulse

0 V

VM

VM

90 %

10 %

tf

tr

tr

tf

001aad983

DUT

VCC

VCC

VI

VO

RT

RL

S1

CL

open

G

Test data is given in Table 10.

Test circuit definitions:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator

CL = Load capacitance including jig and probe capacitance

RL = Load resistance.

S1 = Test selection switch

Fig. 18. Test circuit for measuring switching times

Table 10. Test data

Input

Load

S1 position

VI

tr, tf

CL

RL

tPHL, tPLH

VCC

6 ns

15 pF, 50 pF

1 kΩ

open

74HC191

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 6 — 8 September 2021

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