Nexperia

74LVC11

Triple 3-input AND gate

4. Functional diagram

mna793

3Y

3C

11

3B

10

3A

9

2C

5

2B

4

2A

3

1C

13

1B

2

1A

1

8

2Y

6

1Y

12

Fig. 1. Logic symbol

mna792

12

&

&

&

6

8

13

2

1

5

4

3

11

10

9

Fig. 2. IEC logic symbol

mna794

A

B

C

Y

Fig. 3. Logic diagram for one gate

5. Pinning information

5.1. Pinning

74LVC11

1A

VCC

1B

1C

2A

1Y

2B

3C

2C

3B

2Y

3A

GND

3Y

001aad043

1

2

3

4

5

6

7

8

10

9

12

11

14

13

Fig. 4. Pin configuration for

SOT108-1 (SO14)

74LVC11

1A

VCC

1B

1C

2A

1Y

2B

3C

2C

3B

2Y

3A

GND

3Y

aaa-027674

1

2

3

4

5

6

7

8

10

9

12

11

14

13

Fig. 5. Pin configuration for SOT337-1 (SSOP14) and SOT402-1 (TSSOP14)

001aad044

74LVC11

GND(1)

Transparent top view

2Y

3A

2C

3B

2B

3C

2A

1Y

1B

1C

6

9

5

10

4

11

3

12

2

13

terminal 1

index area

(1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered,

the solder land should remain floating or connected to GND.

Fig. 6. Pin configuration for SOT762-1 (DHVQFN14)

74LVC11

All information provided in this document is subject to legal disclaimers.

©

Nexperia B.V. 2020. All rights reserved

Product data sheet

Rev. 8 — 13 January 2020

2 / 12